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Three-dimensional super-chip integration technology using self-assembly technique

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3 Author(s)
Koyanagi, M. ; Dept. of Bioeng. & Robot., Tohoku Univ., Sendai, Japan ; Fukushima, T. ; Tanaka, T.

We proposed a new three-dimensional (3-D) super-chip integration technology using self-assembly technique. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5 ¿m. We have fabricated 3-D LSI test chips by a super-chip integration technology.

Published in:

Silicon Nanoelectronics Workshop, 2008. SNW 2008. IEEE

Date of Conference:

15-16 June 2008