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A novel VLSI architecture for the full search block matching algorithm using systolic array

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3 Author(s)
Sung Bum Pan ; Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea ; Seung Soo Chae ; Rae-Hong Park

This paper presents a new VLSI architecture of the full search block matching algorithm (FSBMA) using systolic array for motion estimation of moving sequences. The proposed hardware architecture is faster than the conventional ones with lower hardware complexity. It is modeled in very high speed integration circuit hardware description language (VHDL) and simulated to show its functional validity

Published in:

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on  (Volume:2 )

Date of Conference:

12-15 May 1996