Referenced Items are not available for this document.
An efficient IIR PR tree-structured filter bank for HDTV and video signal coding is investigated. Both the arithmetic complexity and the internal chip memory required for the decoder are considerably lower than those of existing FIR synthesis filter banks, while it provides comparable coding performance. Using modern CMOS technology, it is feasible to build the entire decoder on a single chip, thereby facilitating applications such as real-time decoding of compressed HDTV and video signals
Published in:
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
(Volume:2
)
Date of Conference: 12-15 May 1996
- Page(s):
- 632 - 635 vol.2
- Meeting Date :
- 12 May 1996-15 May 1996
- Print ISBN:
- 0-7803-3073-0
- INSPEC Accession Number:
- 5436809
- Conference Location :
- Atlanta, GA
- Digital Object Identifier :
- 10.1109/ISCAS.1996.541804
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
