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A new process technology has been demonstrated that successfully addresses an urgent challenge in silicide technology scaling: the formation of low-resistivity TiSi/sub 2/ on sub-half-micrometer polysilicon lines. The key idea is the use of a TiN cap during the silicide process to minimize contaminants and stress in the film. No complex process steps have been added, and the thermal budget actually has been reduced, allowing for easy integration into standard CMOS technology. The new technology enables low sheet resistance values to be attained for scaled-down TiSi/sub 2/ thicknesses on sub-half-micrometer geometries, and thus, is eminently suited for scaling TiSi/sub 2/ technology.