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In CMOS circuits, for the purpose of isolation, n- and p-channel MOSFETs are normally fabricated on two separate Si areas doped opposite to the n- and p-MOSFETs, respectively. The two Si areas are called twin-tubs. In the conventional CMOS processes, the tub boundaries have a topography height, t/sub tub/, which varies from 100 to 200 nm. With such t/sub tub/, the current I-line lithography tools encounter severe difficulties when printing transistors with dimensions below 0.35 μm. In order to have good dimension control, while not making a major deviation from the conventional process sequence, we seek planarization of the tub boundaries. By utilizing the difference in Si oxidation rates in the linear and parabolic regimes, t/sub tub/ is reduced to 20 nm or less. MOSFETs with 0.3-μm physical lengths and 0.2-μm effective channel lengths are integrated on the planarized twin-tubs. We will discuss the transistor IV and the optimized process parameters which include implant conditions, tub profiles, doping concentrations, temperatures, oxidation times, and oxide thicknesses.