By Topic

Minimization of adders in fast FIR digital filters and its application to filter design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yagyu, M. ; Dept. of Phys. Electron., Tokyo Inst. of Technol., Japan ; Nishihara, A. ; Fujii, M.

This paper proposes fast FIR digital filter structures using the minimal number of adders. Filter coefficients are expressed with canonic signed digit (CSD) code and Hartley's technique is used to minimize the number of adders and subtractors. The proposed filters implemented as wired logic are fast because the structure having the shortest critical path is selected. An algorithm is given to obtain such fast structures. In many examples the critical path length of the filter structures obtained using the proposed method is equal to that of the conventional CSD structures. This paper also presents a new design method of FIR filters using MILP. Utilization of common expressions in Hartley's technique widen the CSD coefficient space. Thus the mixed integer linear programming (MILP) may lead to better frequency responses. Superior frequency responses are actually obtained in many simulations

Published in:

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on  (Volume:2 )

Date of Conference:

12-15 May 1996