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Implementing narrow-band FIR filters using FPGAs

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2 Author(s)
C. H. Dick ; Sch. of Electron. Eng., La Trobe Univ., Melbourne, Vic., Australia ; F. Harris

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. A method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The reduced bit length representation of the re-quantized input samples removes the requirement for a full multiplier in the filter hardware. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. Using a bit-serial approach, a 200 tap narrow-band filter operating at a sample rate of 1.56 MHz has been developed

Published in:

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on  (Volume:2 )

Date of Conference:

12-15 May 1996