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The more advanced microprocessor and ASIC semiconductor packaging currently require several thousand I/O contacts and they are expected to expand contact I/O by 30% in the very near future. Consistent die-to-substrate interface, however, remains the most critical barrier in achieving optimum assembly process yield. Semiconductor suppliers have abandoned the traditional wirebond package assembly for many of these higher I/O products, opting for the more compact die face-down flip-chip attachment methodology. This face-down, direct attachment method significantly reduces the semiconductors package size as well as enhancing product performance. While wire-bond interface may remain the preference for many applications, face-down direct chip attachment has gained popularity for the higher-speed processor and ASIC products. There are a number of factors to consider when selecting an optimal semiconductor package configuration for the newer generations of high density controllers and processors; I/O requirement, package footprint, form factor, thermal dissipation, electrical performance, and cost. This paper will describe a new interconnect solution developed to provide a very uniform array of raised solid copper contact features integrated onto the substrate interposer for mounting very fine pitch bumped flip-chip semiconductor die. This unique raised contact substrate enables semiconductor developers to significantly reduce contact pitch on the die without reducing pad size. Solder bumped die are placed directly onto the raised contact features eliminating the need for solder printing on the package substrate. Mounting the bumped die element on this planer topography solves fundamental issues associated with electro-migration and avoids many of the current assembly process related defects. This is because the raised contact features provide a uniform package interconnect that furnishes a consistent standoff height for improving underfill flow control even with low melt s- olders.