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Assembly of large dies fine pitch Cu/low-k FCBGA package with through silicon via (TSV) interposer

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13 Author(s)
Leong Ching Wai ; Inst. of Microelectron., A*STAR, Singapore, Singapore ; Xiaowu Zhang ; Chai, T.C. ; Srinivas, V.R.
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To eliminate the process of stacked with wire bonding interconnection technology, a through via silicon interposer which is used in stacked dies flip chip are assembled in this study currently. In this study, stack assembly process sequence and the sequence effect on solder joints formation 2nd level joints (between interposer chip and substrate) will be presented. 2nd level joints will be compared between 1× reflow and 2× reflow process. Underfill materials selection for stacked dies large chip package is established with aluminum test vehicle without voids and delamination. Some warpage measurement was carried out on the underfilled package. The optimized underfill process was implemented on the actual cu/low-k test vehicle with through silicon via interposer. Effect of different flux type on the bump voids formation will be discussed. Achieved good assembly yield with optimized flip chip process flow, using selected flux in different flip chip bonders.

Published in:

Electronics Packaging Technology Conference, 2009. EPTC '09. 11th

Date of Conference:

9-11 Dec. 2009