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The challenge of nano packaging requires new nondestructive evaluation (NDE) techniques to detect and characterize very small defects like transportation phenomenon, Kirkendall voids or micro cracks. Imaging technologies with resolutions in the sub-micron range are the desire. But what does nano packaging mean? High end semiconductor industries today deal with functional structures down to 45 nm and below. ITRS roadmap predicts an ongoing decrease of the ?DRAM half pitch? over the next decade. Nano packaging of course is not intended to realize pitches at the nanometer scale, but has to face the challenges of integrating such semiconductor devices with smallest pitch and high pin counts into systems. System integration (SiP, SoP, Hetero System Integration etc.) into the third dimension is the only way to reduce the gap between semiconductor level and packaging level interconnection. The task is not only to identify any impurities on the package surface, but also to look as deep as possible into the package volume. Available non-destructive evaluation (NDE) methods for such kind of packaging are for example X-ray microscopy, X-ray computed tomography, ultrasonic microscopy and thermal microscopy. An overview was presented in. To investigate and discuss the limitations of the current NDE techniques and to find new ways to solve these problems the German government (Federal Ministry of Education and Research - BMBF) supports the research project ?Destructive and non-destructive evaluation techniques to characterize nano-scaled defects in highly miniaturized solder joints -nanoPAL?. The Electronics Packaging Lab and the Center of Microtechnical Manufacturing are the responsible institutions for the non-destructive testing part in this public project and main parts of the content of our presentation are results of this work focused on X-ray nano focus microscopy and nano focus computed tomography. This paper discusses the potentials and the limits of X-ray NDE techniques- , illustrated by crack observation in solder joints, evaluation of micro vias in PCBs and interposers and the investigation of soldering quality of BGAs. The paper presents tomography results with voxel sizes (voxel: smallest gray scale unit / pixel with third dimension (cube)) less than 900nm and gives some information about the practical use of a computed tomography system.
Date of Conference: 9-11 Dec. 2009