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Designing a high speed system with amplitude and phase noise reduction effects

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6 Author(s)
Ki-Jae Song ; Test and Package Development Center, Samsung Electronics ; Jongmin Kim ; Ki-Ryong Woo ; Ilwon Park
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In this paper, we introduce a method for reducing the amplitude and the phase noise to achieve low noise and high speed system. Obtaining a good signal and maintaining the power integrity, by eliminating noise development and propagation are constant requirements. However, the increase of the interconnection complexity in the multilayer PCBs (printed circuit boards) usually creates a questionable noise source that can be caused by either the signal mismatch or the power disturbance. Especially, the SSN (simultaneous switching noise) and coupled noise need to be deliberately examined for reducing the overall noises. After the noise generation and propagation are analyzed, the amplitude and phase noise on the high speed signal will be investigated by using the integrated simulation circuit model (ISCM) technique and according to some related experiments. In this paper, we also propose a multi-PDN structure (M-PS) for minimizing the noise generation and propagation within the wanted frequency band. This method uses an additional core PDN to control the values of the R, L, and C parameters on the equivalent circuit of the system's PDN.

Published in:

Electronics Packaging Technology Conference, 2009. EPTC '09. 11th

Date of Conference:

9-11 Dec. 2009