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Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results

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9 Author(s)
Pares, G. ; MINATEC, CEA-LETI, Grenoble, France ; Minoret, S. ; Lugand, J.F. ; Huet, S.
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Through Silicon Via (TSV) is a one of the more important bricks for 3D stacking and offer different integration approaches. The via-last approach has been first introduced into production. Yet the via-first approach is also currently actively investigated since it has some advantages particularly the use of high conformal deposition materials for isolation and filling of the TSVs enabling higher density of connections or high voltage operations required for certain final product applications. We will show results on process development and integration of 70 ?m deep annular TSVs using tungsten as filling material on a dedicated test chip vehicle. First the complete process flow will be presented. Then, process development work and issues will be addressed. At first we will present developments on the annular trenches opening aiming at favorable slopes and minimum roughness. Deep RIE TSV etching process will be illustrated. For the isolation of the TSV a comparison between SACVD and DHDP deposition oxide will be then discussed. A special focus will be done on W filling sequence using multiple deposition and etch-back steps with different deposition process recipes and a final Chemical Mechanical Polishing (CMP) planarization of the TSVs. The backside process is also presented with the optimization of the back-lapping and CMP process to obtain a stress free silicon surface with no degradation of the TSVs as well as a minimum topology enabling a good back side contact. Backside interconnection is also presented featuring RDL (redistribution layer) and die-to-wafer attach with bumps technology. Then electrical characterizations will be presented. A specific test vehicle was designed to study the TSV density and proximity impact with different number of rings and ring width TSV designs. Daisy chains, specific structures to measure TSV resistance similar to Kelvin structures, interdigitated chains to measure via leakage, and special structures to stress at very high voltag- e (up to 1000 V), were designed. The electrical results from those specific structures will be discussed.

Published in:

Electronics Packaging Technology Conference, 2009. EPTC '09. 11th

Date of Conference:

9-11 Dec. 2009