By Topic

Analytical Phase-Noise Modeling and Charge Pump Optimization for Fractional- N PLLs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Herzel, F. ; IHP, Frankfurt (Oder), Germany ; Osmany, S.A. ; Scheytt, J.C.

We present an analytical frequency-domain phase-noise model for fractional-N phase-locked loops (PLLs). The model includes the noise of the crystal reference, the reference input buffer, the voltage-controlled oscillator (VCO), the loop filter, charge pump (CP) device noise, and sigma-delta modulator (SDM) noise, including its effect on the in-band phase noise. The thermal device noise of the CP and the turn-on time of the CP output current are found to be limiting the in-band phase noise of state-of-the-art synthesizers. Device noise considerations for bipolar transistors and MOSFETs suggest the use of CMOS-only CPs, even in BiCMOS technologies. We present a noise-optimized CMOS CP specifically designed for a dual-loop PLL architecture using two CPs. This PLL architecture keeps the dc output voltage of the noise-relevant CP and the phase-noise spectrum constant, regardless of temperature variations.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:57 ,  Issue: 8 )