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The CIGRE benchmark model for HVDC has been tested for post-fault commutation failures. The observation of the phenomena of post-fault commutation failures and large oscillations in currents and voltages at the inverter and rectifier terminals is explained. These oscillations lead to further commutation failures during recovery and increase the recovery time after original fault clearance. A detailed investigation of control instability is carried out and the components of the control system behaving against expectation are identified. Control modifications are suggested and compared to the control system in the example case in PSCADÂ®/EMTDC. Simulation results are presented and compared with the standard case, which indicate that the suggested control structure exhibits improvements in inverter DC current dynamics to eliminate the risk of post-fault commutation failures due to fault occurrence and clearance at inverter ac bus.