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As CMOS technology scales down into the deep-submicron domain, the cost of design, complexity and customization for Systems-On-Chip (SoCs) is rapidly increasing due to the inefficiency of traditional CAD tools. In this paper we present a new interactive refinement algorithm in high-level synthesis, based on dynamic programming, which maximizes resource optimization in data path. We start by quantifying the properties of the given application C code in terms of control data flow graph (CDFG), available parallelism and other metrics. We then apply designer guided constraints to a data path refinement algorithm for an initial data path. It attempts to reduce the number of the most expensive components while meeting the constraints. The experimental results show that not only the refined data path outperforms data paths refined by other heuristic methods, but also presents lower cost, less overhead and can be generated in less time.