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This paper presents a wideband low-noise amplifier (LNA) architecture that is scalable in terms of the chip area and supply voltage and therefore is expected to offer superior performance with technology scaling. In order to secure low-voltage scalability and allow for potential rail-to-rail operation under an ultralow supply voltage, the CMOS inverter is chosen as the basic amplifier stage. The core of the LNA gain stage comprises two CMOS inverters. To realize wideband operation with area scalability, two band broadening techniques that require neither inductors nor capacitors are adopted. First, to reduce the Miller capacitance, the classic Cherry-Hooper band broadening technique is applied to the CMOS inverterbased amplifier. Second, an active frequency peaking technique is introduced with the use of feedback through another CMOS inverter. The scalability and wideband characteristics of the proposed LNA are confirmed by comparing chips fabricated using 180 nm and 90 nm CMOS process technologies. The LNA in 90 nm CMOS achieved 18.0 dB gain, 0.1-6.8 GHz bandwidth, 3.0-5.5 dB noise figure, and 14.5 mW power dissipation with occupying only 0.0032 mm2, which is 48 % of the 180 nm CMOS LNA area.
Date of Conference: 6-8 Nov. 2009