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60 GHz cascode LNA with interstage matching: performance comparison between 130nm BiCMOS and 65nm CMOS-SOI technologies

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7 Author(s)
Majek, C. ; IMS Lab., Univ. of Bordeaux, Bordeaux, France ; Severino, R.R. ; Taris, T. ; Deval, Y.
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This paper presents a comparative study between two mm-wave technologies from STMicroelectronics: 130 nm BiCMOS and 65 nm CMOS-SOI, through the implementation of a single stage LNA at 60 GHz. Both distributed and lumped design approaches are investigated to work out the best trade-off between silicon saving and performances. The two circuits achieve respectively 12 dB and 6 dB gain, 3.6 dB and 4.5 dB noise figure under 2.5V and 1.2V supply voltage for BiCMOS9MW and CMOS-SOI technologies. The LNA are based on cascode topology with a specific interstage matching for ft and fmax improvement. The current density and transistor sizing are set to perform the lowest NF at 60 GHz, the current consumption is 3.7 mA and 13 mA for BiCMOS9MW and CMOS-SOI LNA respectively.

Published in:

Signals, Circuits and Systems (SCS), 2009 3rd International Conference on

Date of Conference:

6-8 Nov. 2009