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A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager

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5 Author(s)
Uhlig, J. ; Dept. of Neural Circuits & Parallel VLSI-Syst., Univ. of Technol. Dresden, Dresden, Germany ; Schuffny, R. ; Neubauer, H. ; Hauer, J.
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This paper presents a novel ΣΔ-modified MASH architecture (MMA) for a CMOS imager. This architecture makes use of a 1st-order incremental continuous-time sigma-delta modulator with 1.5-bit internal quantizer. It shows key benefits regarding efficient decimation and reduced circuit complexity compared to conventional ΣΔ-architectures. Theory of operation, impact of non-idealities, implementation issues and benefits of the new architecture are depicted. The implementation of the MMA in an 180nm CMOS-Process and simulation results are presented.

Published in:

Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on

Date of Conference:

13-16 Dec. 2009