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This paper presents a novel ΣΔ-modified MASH architecture (MMA) for a CMOS imager. This architecture makes use of a 1st-order incremental continuous-time sigma-delta modulator with 1.5-bit internal quantizer. It shows key benefits regarding efficient decimation and reduced circuit complexity compared to conventional ΣΔ-architectures. Theory of operation, impact of non-idealities, implementation issues and benefits of the new architecture are depicted. The implementation of the MMA in an 180nm CMOS-Process and simulation results are presented.