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With the advent of deep sub-micron technologies, power consumption has become one of the most important research areas in microelectronics. This paper presents a design methodology for power leakage reduction in deep sub-micron digital circuits associated with an automated layout generator. The methodology consists of finding the channel length of transistors in the non-critical paths. The sizing algorithm is basically divided in two steps. First, transistors in the most non-critical paths are sized and then a refinement phase is employed. Different from the standard cell methodology, where several versions of each cell must be inserted in the library before synthesis, in our methodology the layout is generated after the channel length of transistors are defined. Results show that power leakage was reduced to 63% in a set of combinational benchmarks, without timing penalties.