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A new time-based architecture for serial communication links is presented in this paper. The design is based on a low-power pulse-position modulator (PPM) as a transmitter and a low-power, single-cycle-latency time-to-digital converter (TDC) as a receiver. Using the proposed architecture, a 4 Gbps link over a 40 inch FR4 channel has been designed using a 1 GHz input clock signal and performance is compared with a serializer/deserializer (SerDes) link with the same data rate. The proposed architecture concentrates the transmitted signal energy in a significantly lower bandwidth than the conventional SerDes system at the same data rate. This allows simpler circuitry at the receiver side to recover the transmitted data, using smaller chip area and lower power dissipation. The technique can be readily expanded to modulate both edges of the signal, and the clock can also be embedded to avoid the need for a separate clock line.
Date of Conference: 13-16 Dec. 2009