By Topic

Time delay digital tanlock loop with linearized phase detector

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Al-Qutayri, M.A. ; Coll. of Eng., Khalifa Univ. of Sci., Tech. & Res., Sharjah, United Arab Emirates ; Al-Araji, S.R. ; Al-Ali, O.A. ; Anani, N.A.

This paper presents a time delay digital tanlock loop with a linearized phase detector (TDTL-LPD) architecture. This is achieved through replacement of the time delay unit of the TDTL by a variable delay whose phase error is controlled by a feedback mechanism driven by the output of the inverse tan phase detector. The change in this output is proportional to the changes in the input signal frequency of the system. This results in keeping the quadrature relationship between the two channels that make up the TDTL. This linearization of the phase error detector results in the improvement of the system performance when used in communication system applications such as FSK (frequency shift keying) demodulation.

Published in:

Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on

Date of Conference:

13-16 Dec. 2009