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A case study of improving at-speed testing coverage of a gigahertz microprocessor

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5 Author(s)
Zichu Qi ; Key Lab. of Comput. Syst. & Archit., Chinese Acad. of Sci., Beijing, China ; Hui Liu ; Xiangku Li ; Jun Xu
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For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (random access memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing X states for registers, sequential bypass of macros, clock control scheme for inter-clock domains and accurate analysis of exception paths in intra-clock domains. Functional patterns are utilized to further improve the efficiency of the at-speed testing. A novel optimal flow is presented by carefully selecting these techniques. By using the flow, 90% transition fault coverage is achieved. In addition, both the number of patterns and the test time of the transition test are decreased by 15%. The total area overhead is about a few hundreds of AND cells and has little timing impact on the critical paths.

Published in:

Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on

Date of Conference:

13-16 Dec. 2009