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Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits

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5 Author(s)
Figueiredo, M. ; Dept. of Electr. Eng., Univ. Nova de Lisboa, Monte da Caparica, Portugal ; Michalak, T. ; Goes, J. ; Gomes, L.
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This paper presents an improved clock-phase generator, able to provide two non-overlapping phases, with an accurate phase shift of 180 degrees. The circuit relies on a modified version of the classic NAND-based bi-phase clock generator but uses an equalizing transmission gate together with dedicated self-biased logic. Simulation results over PVT corners show that, when compared with the original bi-phase clock generator, the proposed circuit exhibits a reduction in the spread of the phase-skew error by a factor higher than 2.4 whilst dissipating similar power. Moreover, the proposed circuit does not require any kind of calibration.

Published in:

Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on

Date of Conference:

13-16 Dec. 2009