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A fine pitch and high aspect ratio bump fabrication process for flip-chip interconnection

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2 Author(s)
Yamada, H. ; Labs. of Mater. & Devices, Toshiba Corp., Yokohama, Japan ; Saito, M.

This paper describes the fabrication process for the finest pitch and highest aspect ratio bump arrays reported so far. Particularly noteworthy is the development of a new microstructural resist patterning technique in which electroplating is used to form the bumps. The alkaline solubility and dissolution effect parameter of the resist were evaluated to obtain the precise microstructural pattern. The finest pitch and highest aspect ratio resist patterns fabricated had a 10 μm pitch with a 5 μm diameter and a 50 μm height, and they were arranged 5 μm apart from each other

Published in:

Electronic Manufacturing Technology Symposium, 1995, Proceedings of 1995 Japan International, 18th IEEE/CPMT International

Date of Conference:

4-6 Dec 1995