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Test data compression is a basic necessity for today's test methodology with reference to test cost and test time. This paper presents a compression/decompression scheme based on frequency dependant bit appending of test vector used with statistical codes. In the proposed scheme, the emphasis is not only on data compression but it aims the data compression with a smaller amount of silicon area overhead for on chip decoder. We have observed that when the number of bits per test vector is prime number or multiplication of prime number (particularly multiplied by 2 or 3), statistical codes gives a large area overhead. The proposed scheme of frequency dependant bit appending (FDBA) shows that in such cases, if we append few bits at the end of test vector before compression, it improves % compression with very less area overhead. With ISCAS benchmark circuits, it has been shown that when the proposed scheme is applied with statistical coding method, it not only improves % compression, but the area overhead is reduced a lot compared to the base statistical method.