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On-chip communication architecture plays an important role in determining the overall performance of the system-on-chip (SoC) design. In the resource sharing mechanism of SoC, the communication architecture should be flexible to offer high performance over a wide range of traffic. The low priority components may suffer from starvation, while high priority components may have large latency. The conventional bus-distribution algorithms, such as the static fixed priority and the round robin, show several defects that are bus starvation, and low system performance because of bus distribution latency in a bus cycle time. The lottery bus arbiter scheme like static & dynamic are already shows efficiency over traditional methods. AMBA (advanced microcontroller bus architecture) defines both bus specification and a technology independent methodology for designing, implementing and testing customized high-integration embedded controllers. Here author presents AMBA using dynamic lottery bus arbiter. The architecture is based on a probability bus distribution algorithm. The architecture is model in VHDL and some simulation results are presented.