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Drain current model for thin-film transistors with interface trap states

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3 Author(s)
Tsuji, H. ; Division of Electrical, Electronic and Information Engineering, Osaka University, Suita, Osaka 565-0871, Japan ; Kamakura, Yoshinari ; Taniguchi, K.

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.3289439 

A surface-potential-based drain current model for thin-film transistors (TFTs) is presented. In this model, the influence of traps located at the gate-oxide/silicon interface is accounted for to reproduce the gradual increase in the subthreshold current. The model uses a single equation that includes both drift and diffusion current components to describe the drain current in all operation regions. Calculations using the model produce results that are in good agreement with the measured current-voltage characteristics of polycrystalline silicon TFTs with large grains.

Published in:

Journal of Applied Physics  (Volume:107 ,  Issue: 3 )