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The new test wrapper design for core testing in packet-switched micro-network on chip

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2 Author(s)
Aghaei, B. ; Dept. of Eng., Islamic Azad Univ., Malekan, Iran ; Babaei, S.

Recent advances in packet-switched micro-network on chip arise great challenges in test and testability issues. This paper presents a novel test wrapper design for embedded cores in NoC. This wrapper uses functional ports for test data transmission. We assembled proposed test wrapper on a processor during hierarchical simulation. Clearly, simulation results show our proposed wrapper works correctly.

Published in:

Power Electronics and Intelligent Transportation System (PEITS), 2009 2nd International Conference on  (Volume:2 )

Date of Conference:

19-20 Dec. 2009