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This paper presents a cost-efficient technique to jointly use circuit- and architecture-level techniques to protect an embedded processor's register file against soft errors. The basic idea behind the proposed technique is robust register caching (RRC), which creates a cache of the most vulnerable registers within the register file in a small and highly robust cache memory built from circuit-level single-event-upset-protected memory cells. To guarantee that the most vulnerable registers are always stored in the robust register cache, the average number of read operations during a register's lifetime is used as a metric to guide the cache replacement policy. A register is vulnerable to soft errors when it holds a value that will be used in subsequent cycles. Consequently, while a register value is stored in the register cache, it is robust against single- and multiple-bit upsets. To minimize the power overhead of the RRC, the clock-gating technique is efficiently exploited by the main register file, resulting in significantly reduced power consumption. The RRC was experimentally evaluated using the LEON processor for two benchmarks, namely, the MiBench embedded benchmark suite and the SPEC CPU2006 general-purpose benchmark. Our experimental results show that if the cache size is selected appropriately, the architectural vulnerability factor (AVF) of the register file is significantly reduced while also offering the benefits of low power, area, and performance overheads.
Device and Materials Reliability, IEEE Transactions on (Volume:10 , Issue: 2 )
Date of Publication: June 2010