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New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

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2 Author(s)
Ming-Dou Ker ; Dept. of Electron. Eng., I-Shou Univ., Kaohsiung, Taiwan ; Cheng-Cheng Yen

A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18-μm complementary-metal-oxide-semiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

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Industrial Electronics, IEEE Transactions on  (Volume:57 ,  Issue: 10 )