Skip to Main Content
With the advent of sophisticated multi-processor computing systems, the design of bus arbitration circuits has become a critical issue; in fact, performance of the system heavily depends on how efficiently accesses to the bus are regulated by the bus contention resolution mechanism. In this paper we present experimental data on the implementation of an easily scalable mixed centralized/distributed arbitration circuit realizing different dynamic priority assignment schemes.
Signals, Systems and Computers, 1995. 1995 Conference Record of the Twenty-Ninth Asilomar Conference on (Volume:1 )
Date of Conference: Oct. 30 1995-Nov. 1 1995