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Performance evaluation for optical network-on-chip interconnect architectures

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2 Author(s)
Wang, Shiqing ; State Key Lab of ISN, Xidian University, Xi''an, China 710071 ; Huaxi Gu

A large number of IP cores will be included in the future systems-on-chip (SoC). Traditional bus-based architectures are no longer suitable for modern chip design, since it is difficult to expand, consumes much power and takes much area. Network-on-chip (NoC), which employs networks to replace buses as a scalable global communication platform, has been proposed to cope with these problems. However, limited bandwidth, long delay and high power consumption will become bottlenecks as NoC scales to large sizes. Based on silicon optical interconnect, optical network-on-chip (ONoC) can offer significant bandwidth and power advantages, which provides a promising solution to overcome these limitations. In this paper, we simulated and compared several ONoCs based on the topologies including 2D Mesh, 3D Mesh, 2D Fat Tree(FT) and 2D Butterfly Fat Tree(BFT) in terms of the end-to-end delay and network throughput. The results showed that 3D Mesh has the best performance among the listed topologies.

Published in:

Communications and Photonics Conference and Exhibition (ACP), 2009 Asia  (Volume:2009-Supplement )

Date of Conference:

2-6 Nov. 2009

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