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A hierarchical multiprocessor scheduling system for DSP applications

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3 Author(s)
Pino, J.L. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Bhattacharyya, S.S. ; Lee, E.A.

This paper discusses a hierarchical scheduling framework which reduces the complexity of scheduling synchronous data flow (SDF) graphs onto multiple processors. The core of this framework is a clustering algorithm that decreases the number of nodes before expanding the SDF graph into a precedence directed acyclic graph (DAG). The internals of the clusters are then scheduled with uniprocessor SDF schedulers which can optimize for memory usage. The clustering is done in such a manner as to leave ample parallelism exposed for the multiprocessor scheduler. We have developed the SDF composition theorem for testing if a clustering step is valid. The advantages of this framework are demonstrated with several practical, real-time examples.

Published in:

Signals, Systems and Computers, 1995. 1995 Conference Record of the Twenty-Ninth Asilomar Conference on  (Volume:1 )

Date of Conference:

Oct. 30 1995-Nov. 1 1995