By Topic

Dynamic Quadrant Swapping Scheme Implemented in a Post Conversion Block for I, Q Mismatch Reduction in a DQPSK Receiver

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Lam, N. ; Electr. & Comput. Eng. Dept., Univ. of Waterloo, Waterloo, ON, Canada ; Leung, B.H.

This paper presents a new dynamic quadrant swapping scheme that reduces crosstalk due to I/Q path mismatch for DQPSK receiver. The scheme reduces crosstalk by selectively transforming/swapping the I, Q components of the received symbols. The scheme's effectiveness is demonstrated by applying it to the IF digitizer part of the receiver. In the IF digitizer the incoming IF (first IF) signal is mixed and then converted to two digital signals, the I and Q signals, both at a second IF. These digital signals are then fed into a post conversion block. In this block dynamic quadrant swapping is applied, which reduces the crosstalk. Using an IF digitizer that includes two separate mixers with two separate low pass sigma-delta modulators for I and Q paths, the scheme's effectiveness is tested. Both simulation results and measured results show a significant improvement in image rejection ratio and BER, when the scheme is applied. With a SNR of 10.8 dB, at a 160.16 MHz incoming IF, and with a data rate of 36 kbps, the scheme improves the measured BER from 4.2 × 10 to 1.4 × 10- 3. At a 10 MHz incoming IF, and with a data rate of 2 kbps, the scheme improves the measured image rejection ratio from 41 dB to 65 dB and the measured BER from 1.3 × 10-3 to 0.7 × 10-3. The post conversion block is layout in 0.09 ¿m CMOS technology. It occupies an area of 0.00092 mm2, and is simpler than previous reported schemes. The IF digitizer is fabricated in 0.35 ¿m CMOS technology.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 2 )