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A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO

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6 Author(s)
Wei Liu ; Shenzhen Grad. Sch., Peking Univ., Shenzhen, China ; Wei Li ; Peng Ren ; Chinglong Lin
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An all-digital phase-locked loop (ADPLL) with all components working with time interval or period signals is demonstrated. The ADPLL consists mainly of a free-running ring oscillator (FRO), a time to digital converter (TDC), a digitally controlled oscillator (DCO), a digital divider and a digital loop filter. In the proposed architecture, the TDC and DCO have an equal time resolution from the common FRO. The digital divider keeps the loop gain constant when the frequency multiplication factor changes. As a result, the ADPLL is inherently stable regardless of the variations of the process, supply voltage and temperature (PVT). The ADPLL is fabricated in 0.13 ¿m CMOS process. Measurement results show that it works well over wide operation conditions, with the input frequencies ranging from 37.5 KHz to 25 MHz, frequency multiplication factors from 10 to 255, output frequencies from 10 MHz to 500 MHz, and supply voltages from 0.6 V to 1.6 V.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 2 )