By Topic

Investigation of Capacitorless Double-Gate Single-Transistor DRAM: With and Without Quantum Well

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ertosun, M.G. ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; Saraswat, K.C.

We characterize and optimize double-gate single-transistor DRAM via extensive simulations. We propose a new kind of DRAM, namely, the single-transistor (1T) quantum well (QW) DRAM, which has a ¿storage pocket¿ for holes within the body. This memory employs the QW as a way of energy band engineering to introduce the storage pocket within the body of the device, which also gives the opportunity to engineer spatial hole distribution within the device, which is not possible with the conventional 1T DRAMs. With this ¿storage pocket¿ and spatial hole distribution engineering approach, we demonstrate improvement in the drain current (I d) difference between the reads of two states of the memory and, hence, improvement in sense margin and scalability characteristics. Furthermore, it is found that the use of SiGe instead of pure germanium to form the QW has added advantages in terms of retention, erase scheme, and fabrication.

Published in:

Electron Devices, IEEE Transactions on  (Volume:57 ,  Issue: 3 )