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Browse Journals & Magazines > Photonics Technology Letters, ...> Volume:22 Issue:8 Help

Photonic Device Layout Within the Foundry CMOS Design Environment

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2 Author(s)
Orcutt, J.S. ; Res. Lab. of Electron., Massachusetts Inst. of Technol., Cambridge, MA, USA ; Ram, R.J.

A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.

Published in:
Photonics Technology Letters, IEEE  (Volume:22 ,  Issue: 8 )

Date of Publication: April15, 2010

Page(s):
544 - 546
ISSN :
1041-1135
INSPEC Accession Number:
11180069
Digital Object Identifier :
10.1109/LPT.2010.2041445
Product Type:
Journals & Magazines
Date of Publication :
02 February 2010
Date of Current Version :
18 March 2010
Issue Date :
April15, 2010
Sponsored by :
IEEE Photonics Society

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