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A simple new phase frequency detector design is presented in this paper. Falling-edge PFD uses only 12 transistors and preserves the main characteristics of the conventional PFD. It is implemented using Silterra 0.18 Â¿m CMOS process. It consumes 6.6 Â¿W when operating at 50 MHz clock frequency with 1.8 V voltage supply. It has free dead zone and operates up to 2.5 GHz. It can be used in high speed and low power consumption applications. A single ended switch at source charge pump is presented as well. It is compatible with the FE-PFD outputs characteristics.
Design and Test Workshop (IDT), 2009 4th International
Date of Conference: 15-17 Nov. 2009