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In this paper, we present an efficient technique for mapping a set of IP-cores onto tiles of a network-on-chip (NoC). Our constraints are power dissipation, communication bandwidth, and routing resources. To evaluate the proposed scheme, the technique has been applied to some real applications and random task graphs with different sizes of mesh topologies. The results of the mapping technique are compared with schemes based on the genetic algorithm, EPAM technique, and random mapping. The comparison shows that the extra communication power consumptions compared to an ideal mapping are up to 20% and 86% less compared to those of the genetic algorithm and random mapping for real applications. The extra power consumptions are about the same when compared to those of the EPAM scheme. In general, the runtime of the proposed algorithm is considerably lower than those of GA and EPAM techniques for large NoCs, making the technique an efficient mapping scheme.
Design and Test Workshop (IDT), 2009 4th International
Date of Conference: 15-17 Nov. 2009