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Lithography and stress variations are two dominant effects impacting the functionality and performance of designs at 65 nm and below. In addition; proximity effects from neighboring cells, significantly influence the lithography process and stress variations values. Therefore studying the design context has to be considered in any variability-aware circuit analysis. This paper discusses the importance of accounting for context effects when characterizing IC manufacturing process variability. A methodology to extract a context-aware variability for digital standard cells is presented by monitoring the differences in the physical and electrical parameters when the standard cell is placed in different contexts. Industrial 65 nm and 45 nm standard cell libraries have been used in our experiments.