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Area and delay optimization for Networks-on-Chip architectures using Genetic Algorithms

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4 Author(s)
Morgan, A.A. ; Dept. of Electr. & Comput. Eng., Univ. of Victoria, Victoria, BC, Canada ; Elmiligi, H. ; El-Kharashi, M.W. ; Gebali, F.

Networks-on-Chip (NoC) architecture design faces a trade-off between cost and performance. In this paper, we target one aspect of this trade-off: area versus average delay. The NoC architecture generation is formulated as a two-objective optimization problem and a Genetic Algorithm (GA)-based technique is used to solve it. According to the application requirements and the design constraints, the optimization process could be controlled by the designer by specifying weight factors for area and delay. As a proof of concept, our technique is applied to a case study of an Audio Video (AV) application. Results show that the proposed solution is a promising way to achieve the best architecture with respect to both delay and area.

Published in:

Design and Test Workshop (IDT), 2009 4th International

Date of Conference:

15-17 Nov. 2009