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Design of a 21 GHz UWB differential low noise amplifier using .13µm CMOS process

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4 Author(s)
Rashid, S.M.S. ; Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh ; Roy, A. ; Ali, S.N. ; Rashid, A.B.M.H.

This paper presents the design of a 21 GHz UWB differential low noise amplifier. The circuit is designed in IBM .13 μm CMOS process and is simulated in Cadence Spectre. The forward gain of the circuit is 9.72 dB at 21 GHz with a bandwidth of 4 GHz (from 19 GHz to 23 GHz). Reverse isolation is less than -26.4 dB and the input-output matching parameters are -26 dB and -19.5 dB respectively. Noise figure of the LNA is 4.4 dB at the center frequency. The amplifier is driven by a 1.2 V power supply and consumes only 20.76 mW power. To the best of the authors' knowledge, UWB differential low noise amplifier operating above 20 GHz is rarely reported.

Published in:

Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on

Date of Conference:

14-16 Dec. 2009

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