Efficient multiplierless designs for 1-D DWT using 9/7 filters based on distributed arithmetic

In this paper, we present a distributed arithmetic (DA) formulation of the computation of discrete wavelet transform (DWT) using 9/7 filters, and mapped that into bit-parallel and bit-serial architectures for high-throughput and low-hardware implementations, respectively. The bit-serial structure processes the bit-slices of input vector in serial manner for low-hardware solution, while the bit-parallel structure processes all the bit-slices in parallel for high-throughput computation. The bit-parallel structure has 100% hardware utilization efficiency. Compared with the existing multiplierless structures, the proposed structures offer significantly higher throughput rate and involve less area-delay product.