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A high-performance multibit-flipping algorithm for LDPC decoding

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2 Author(s)
Jui-Hui Hung ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Sau-Gee Chen

For LDPC decoding, bit-flipping (BF) algorithms are much simpler than the min-sum algorithms (MSA). However, BF algorithms have the disadvantages of poorer performances and higher iteration counts than MSA. This paper introduces the concepts of low correlation search and culprit vote to further improve the efficiency of the existing BF algorithms. High decoding performances and low iteration number are achieved by flipping those bits with low correlation as much as possible and introducing an additional syndrome vote procedure. As a result, the proposed algorithm can achieve significant decoding performance which is very close to the min-sum algorithm (MSA) but with much lower computation complexity.

Published in:

Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on

Date of Conference:

14-16 Dec. 2009

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