By Topic

Symbolic techniques for statistical timing analysis of RCL mesh networks with resistor loops

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Zhigang Hao ; Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China ; Guoyong Shi

A symbolic moment calculator for recursive moment computation of RCL interconnect networks involving resistor loops is proposed. Using the tearing technique, the network can be partitioned into a spanning tree and a set of resistor links. Special data structures for symbolic moment analysis are proposed. Applications of this structural computation methodology to symbolic reduced order modeling and statistical timing analysis of mesh networks are investigated.

Published in:

Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on

Date of Conference:

14-16 Dec. 2009