By Topic

Modeling of a 14-bit, 100-MS/s pipelined ADC with digital nonlinearity calibration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Xuan Wang ; Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China ; Junxiao Chen ; Lenian He

This paper describes a digital calibration scheme for pipelined analog-to-digital converters (ADCs). The proposed method corrects the nonlinearity caused by finite gain and bandwidth of interstage operational amplifiers as well as the capacitors mismatch in multiplying digital-to-analog converters. The proposed calibration technique takes the advantages of both foreground and background calibration schemes. A behavior simulation is carried out to verify the proposed calibration scheme. Simulation results revealed that for a 14 bit, 100 MS/s pipelined ADC with 0.1% capacitor mismatch, the INL could be limited within ±1.2 LSB and a 76.8 dB SNDR is achieved, due to proposed digital calibration technique.

Published in:

Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on

Date of Conference:

14-16 Dec. 2009