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Modeling of a 14-bit, 100-MS/s pipelined ADC with digital nonlinearity calibration

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3 Author(s)
Xuan Wang ; Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China ; Junxiao Chen ; Lenian He

This paper describes a digital calibration scheme for pipelined analog-to-digital converters (ADCs). The proposed method corrects the nonlinearity caused by finite gain and bandwidth of interstage operational amplifiers as well as the capacitors mismatch in multiplying digital-to-analog converters. The proposed calibration technique takes the advantages of both foreground and background calibration schemes. A behavior simulation is carried out to verify the proposed calibration scheme. Simulation results revealed that for a 14 bit, 100 MS/s pipelined ADC with 0.1% capacitor mismatch, the INL could be limited within ±1.2 LSB and a 76.8 dB SNDR is achieved, due to proposed digital calibration technique.

Published in:

Proceedings of the 2009 12th International Symposium on Integrated Circuits

Date of Conference:

14-16 Dec. 2009