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A 12-bit — 35-MS/s pipeline ADC with dynamic element matching correction for ILC/CALICE integrated read-out

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3 Author(s)
Rarbi, F. ; CNRS/IN2P3 Lab., Univ. de Grenoble, Grenoble, France ; Dzahini, D. ; Gallin-Martel, L.

A low power 12 bits analog to digital converter is a critical part of a fully integrated readout system for the next ILC ECAL. We present here a new design of 12-bit ADC up to 35-MS/s using a pipelined architecture in a CMOS 0.35 m process. The first front-end stage of 2.5 bits includes an efficient dynamic element matching scheme permitting to average its gain errors. The back-end converter is a set of seven 1.5 bit stages followed by a 3 bit full flash. The dynamic range covered is 2V. The analog part of the converter can be quickly (in a couple of s) switched to a standby mode that reduces the DC power dissipation. The size of this converters layout including the output pads is 1.4mm??1.3mm, and the total power dissipation is only 45mW.

Published in:

Nuclear Science Symposium Conference Record (NSS/MIC), 2009 IEEE

Date of Conference:

Oct. 24 2009-Nov. 1 2009

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