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A low-cost coincidence system with capability of multiples coincidence for high count-rate TOF or non-TOF PET cameras using hybrid method combining AND-logic and Time-mark technology

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8 Author(s)
Chao Wang ; Dept. of Exp. Diagnostic Imaging, Univ. of Texas, Houston, TX, USA ; Hongdi Li ; Baghaei, H. ; Yuxuan Zhang
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A low-cost fully digital FPGA-based high count-rate coincidence system has been developed for TOF (Time of Flight) and non-TOF PET cameras. Using a hybrid of AND-logic and Time-mark technology produced both excellent timing resolution and high processing speed. In this hybrid architecture, every gamma event was synchronized by a 125 MHz system clock and generating a trigger associated with a time-mark given by an 8-bit high-resolution TDC (68.3ps/bin). AND-logic was applied to the synchronized triggers for real-time raw sorting of coincident events. An efficient FPGA based Time-mark fine-sort algorithm is used to select all the possible coincidence events within the preset coincidence time window. This FPGA-based coincidence system for a modular PET camera offers reprogrammable flexibility and expandability, so the coincidence system is easily employed, regardless of differences in the scale of the PET camera detector setup. A distributed processing method and pipeline technology were adopted in the design to obtain very high processing speed. In this design, both prompt and time-delayed accidental coincidences are simultaneously processed in real time. The real-time digital coincidence system supports coincidence in 2 to 12 detector module setups, capable of processing 72 million single events per second with no digital data loss and captures multiple-event coincidence for better imaging performance evaluation. The coincidence time window-size and time-offset of each coincidence event pair can be programmed independently in 68.3 ps increments (TDC LSB) during the data acquisition in different applications to optimize the signal-to-noise ratio. The complex coincidence system is integrated in one circuit board with 1.5 Gbps fiber optic interface. We demonstrate the system performance using the actual circuit and Monte Carlo simulations.

Published in:

Nuclear Science Symposium Conference Record (NSS/MIC), 2009 IEEE

Date of Conference:

Oct. 24 2009-Nov. 1 2009