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As the microprocessor speed increases from 500MHz to 1GHz and beyond, SOC designers are forced to innovate new schemes in their use of cache memory for high speed access. In this paper, clock to wordline path delay is optimized using a novel circuit design technique. Using this novel circuit, clock to word line path delay is optimized by 2.5 times at worst case corner. For a typical memory instance frequently used in cache memories whose access time is of the order of 800ps and where read and write operation occurs in the same clock cycle, overall access time is improved by 18% at worst case corner. For this case, write margin is improved by 2.26 times at worst case corner for write operation. A decoding scheme is also discussed in this paper which describes how to choose the best pre-decoding and post-decoding schemes based on minimum pre-decoded lines, minimum stack size in post decoder and maximum granularity of x-decoders.