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A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms

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4 Author(s)
Ahuja, S. ; FERMAT Lab., Virginia Tech, Blacksburg, VA, USA ; Wei Zhang ; Lakshminarayana, A. ; Shukla, S.K.

Hardware co-processors are used for accelerating specific compute-intensive tasks dedicated to video/audio codec, encryption/decryption, etc. Since many of these data-processing tasks already have efficient software algorithms, one could reuse those to synthesize the co-processor IPs. However, such software algorithms are usually sequential and written in C/C++. High-level Synthesis (HLS) helps in converting software implementation to register transfer level (RTL) hardware design. Such co-processor based systems show enhanced performance but often have greater power/energy consumption. Therefore, the automated synthesis of such accelerator IPs must be power-aware. Downstream power savings features such as clock-gating are unknown during HLS. Designer is forced to take such power-aware decisions only after logic synthesis stage, causing an increase in design time and effort. In this paper, we present a design automation solution to facilitate various granularities of clock-gating at high-level C description of the design.

Published in:

VLSI Design, 2010. VLSID '10. 23rd International Conference on

Date of Conference:

3-7 Jan. 2010